? 2000 california micro devices corp. all rights reserved. 4/00 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 1 california micro devices PACVGA200 vga port companion circuit features ? 7 channels of esd protection for all vga port connector pins meeting iec-61000-4-2 level-4 esd requirements (8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines, 4pf typical ? ttl to cmos level-translating buffers with power down mode for hsync and vsync lines ? 75 w termination resistors for video lines (matched to 1%?typ.) ? bi-directional level shifting n-channel fets provided for ddc_clk & ddc_data channels ? compact 24-pin qsop package c0641299 PACVGA200? is a trademark of california micro devices corp. pin diagram schematic diagram product description the PACVGA200 incorporates 7 channels of esd protection for all signal lines commonly found in a vga port. esd protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with iec-1000-4- 2 level-4 esd protection (8kv contact discharge). when a channel is subjected to an electrostatic discharge, the esd current pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated. separate positive supply rails are provided for the video, ddc and sync channels to facilitate interfacing with low voltage video controller ics and provide design flexibility in multi-supply-voltage environments. two non-inverting drivers provide buffering for the hsync and vsync signals from the video controller ic (sync1, sync2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc4 . these drivers have nominal 60 w output impedance to match the characteristic impedance of the hsync & vsync lines of the video cables typically used in pc applications. two n-channel fets provide the level shifting function required when the ddc controller is operated at a lower supply voltage than the monitor. three 75 w termination resistors suitable for terminating the video signals from the video dac are also provided. these resistors have separate input pins to allow insertion of additional emi filtering, if required, between the termination point a nd the esd protection diodes. these resistors are matched to better than 2% for excellent signal level matching for the r/g/b signals. when the pwr_up input is driven low the sync inputs can be floated without causing the sync buffers to draw any current from the v cc3 supply. when the pwr_up input is low the sync outputs are driven low. an internal diode (d1 in schematic below) is also provided so that v cc3 can be derived from v cc4 , if desired, by connecting v cc3 to v_bias. in applications where v cc4 may be powered down, diode d1 blocks any dc current paths from the ddc_out pins back to the powered down v cc4 rail via the top esd protection diodes. 24-pin qsop package
?2000 california micro devices corp. all rights reserved. 4/00 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 2 california micro devices PACVGA200 s g n i t a r m u m i x a m e t u l o s b a r e t e m a r a pg n i t a rt i n u v 1 c c v , 2 c c v , 3 c c v & 4 c c e g a t l o v y l p p u s0 . 6 + , 5 . 0 - d n gv t n e r r u c d r a w r o f 1 d e d o i d0 0 1a u : s t u p n i t a e g a t l o v c d v 3 _ o e d i v , 2 _ o e d i v , 1 _ o e d i vv , 5 . 0 - d n g 1 c c 5 . 0 +v 3 _ m r e t , 2 _ m r e t , 1 _ m r e t0 . 6 + , 0 . 6 -v 2 n i _ c d d , 1 n i _ c d dv , 5 . 0 - d n g 2 c c 5 . 0 + 2 t u o _ c d d , 1 t u o _ c d dv , 5 . 0 - d n g 3 c c 5 . 0 +v 2 n i _ c n y s , 1 n i _ c n y sv , 5 . 0 - d n g 4 c c 5 . 0 +v : e r u t a r e p m e t e g a r o t s0 5 1 + o t 0 4 - o c t n e i b m a g n i t a r e p o0 7 + o t 0 o c n o i t a p i s s i d r e w o p e g a k c a p0 . 1w note 1: these parameter applies only to the hsync and vsync channels. note 2: per the iec-61000-4-2 international esd standard, level 4 contact discharge method. v cc1 , v cc3 and v cc4 must be bypassed to gnd via a low impedance ground plane with a 0.2uf, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pins and gnd. esd pulse can be positive or negative with respect to gnd. applicable pins are: video_1, video_2, video_3, sync_out1, sd1, sync_out2, sd2, ddc_out1 and ddc_out2. all other pins are esd protected to the industry standard 2kv per the human body model (mil-std-883, method 3015). note 3: this parameter is guaranteed by design and characterization. s c i t s i r e t c a r a h c g n i t a r e p o l a c i r t c e l e ) e s i w r e h t o d e i f i c e p s s s e l n u s n o i t i d n o c g n i t a r e p o r e v o ( l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a mt i n u i 1 c c v 1 c c t n e r r u c y l p p u sv 1 c c t a s t u p n i o e d i v ; v 5 =v 1 c c d n g r o0 1a u i 3 , 2 c c v 2 c c v , 3 c c t n e r r u c y l p p u sv 2 c c v = 3 c c v 5 =0 1a u i 4 c c v 4 c c t n e r r u c y l p p u sv 4 c c v r o d n g t a s t u p n i c n y s ; v 5 = 4 c c ;0 1a u v t a n i p p u _ r w p ; 4 c c d e d a o l n u s t u p t u o c n y s v 4 c c p u _ r w p ; v 0 . 3 t a s t u p n i c n y s ; v 5 =0 0 2a u v t a n i p 4 c c d e d a o l n u s t u p t u o c n y s ; v 4 c c c n y s ; d n g t a t u p n i p u _ r w p ; v 5 =0 1a u d e d a o l n u s t u p t u o v s a i b v s a i b e g a t l o v t i u c r i c n e p ov m o r f n w a r d t n e r r u c l a n r e t x e o n s a i b n i pv 4 c c 8 . 0 -v r t e c n a t s i s e r n o i t a n i m r e t o e d i v 5 2 . 1 75 75 7 . 8 7 w r t g n i h c t a m e c n a t s i s e r 12% v h i e g a t l o v t u p n i h g i h c i g o l 1 v 4 c c v 0 . 5 =0 . 2v v l i e g a t l o v t u p n i w o l c i g o l 1 v 4 c c v 0 . 5 =8 . 0v v h o e g a t l o v t u p t u o h g i h c i g o l 1 i h o v , a m 4 - = 4 c c v 0 . 5 =4 . 4v v l o e g a t l o v t u p t u o w o l c i g o l 1 i l o v , a m 4 = 4 c c v 0 . 5 =4 . 0v r b r , p e u l a v r o t s i s e rv , p u _ r w p 3 c c v 0 . 5 =5 . 012m w r c v 2 c c r o t s i s e r n w o d - l l u pv 2 c c v 0 . 3 =5 . 05 . 13m w i n t n e r r u c t u p n i s t u p n i o e d i vv 1 c c v ; v 5 = n i v = 1 c c d n g r o1 m a s t u p n i c n y s v , c n y s hv 4 c c v ; v 5 = n i v = 4 c c d n g r o1 m a i f f o l e v e l , t n e r r u c e g a k a e l e t a t s f f ov ( 2 c c v - n i _ c d d )< v ; v 4 . 0 c d d _ t u o v = 2 c c 0 1 m a t e f n g n i t f i h sv ( 2 c c v - t u o _ c d d )< v ; v 4 . 0 c d d _ n i v = 2 c c 0 1 m a v n o l e v e l s s o r c a p o r d e g a t l o vv 2 c c v ; v 5 . 2 = s i , d n g = s d a m 3 =5 1 . 0v n o d e n r u t n e h w t e f n g n i t f i h s c n i e c n a t i c a p a c t u p n i 3 3 _ o e d i v , 2 _ o e d i v , 1 _ o e d i vv 1 c c v ; v 0 . 5 = n i z h m 1 t a d e r u s a e m ; v 5 . 2 =0 . 4f p v 1 c c v ; v 5 . 2 = n i z h m 1 t a d e r u s a e m ; v 5 2 . 1 =5 . 4 t h l p y a l e d n o i t a g a p o r p h - l s r e v i r d c n y sc l v ; f p 0 5 = c c t t u p n i ; v 5 = r t d n a f < s n 582 1s n t l h p y a l e d n o i t a g a p o r p l - h s r e v i r d c n y sc l v ; f p 0 5 = c c t t u p n i ; v 5 = r t d n a f < s n 582 1s n t r t , f s e m i t l l a f & e s i r t u p t u o s r e v i r d c n y sc l v ; f p 0 5 = c c t t u p n i ; v 5 = r t d n a f < s n 57s n v d s e e g a t l o v d n a t s h t i w d s e 3 , 2 v 1 c c v = 3 c c v = 4 c c v 5 =8 v k
? 2000 california micro devices corp. all rights reserved. 4/00 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 3 california micro devices PACVGA200 typical connection diagram a resistor may be necessary between the v cc3 pin and ground if protection against a stream of esd pulses is required while the PACVGA200 is in the power-down state. the value of this resistor should be chosen such that the extra charge deposited into the v cc3 bypass capacitor by each esd pulse will be discharged before the next esd pulse occurs. the maximum esd repetition rate specified by the iec-61000-4-2 standard is one pulse per second. when the PACVGA200 is in the power-up state, an internal discharge resistor is connected to ground via an fet switch for this purpose. for the same reason, v cc1 and v cc4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. gnda, the reference voltage for the 75r resistors is not connected internally to gndd and should ideally be connected to the ground of the video dac ic. t s r a d n a n o i t a m r o f n i g n i r e d r o t r a p d e g a k c a pr e b m u n t r a p g n i r e d r o s n i pe l y t sg n i k r a m t r a p 4 2p o s qq 0 0 2 a g v c a p when placing an order please specify desired shipping: tubes or tape & reel.
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